As microfabrication progresses, many transistors have become able to be integrated on the same chip, and also circuits with many functions have become able to be mounted on the same chip. On-chip memory having a memory and a processor mixed on the same chip is superior in both of data transfer rate and power consumption, compared with the case where memory is separately mounted on another chip. In particular, as mobile devices including cellular phone and PDA (Personal Digital Assistance) become more sophisticated in functionality, compatibility between high functionality and low power consumption is valued, and therefore on-chip memory will play an important role.
For on-chip memory, SRAM (Static Random Access Memory) is dedicatedly used in view of consistency in manufacturing process with logic transistors.
M. Yamaoka et al, IEEE International Solid-State Circuits Conferences, pp. 494-495, (2004) discloses a technology regarding on-chip low power in SRAM.
On the other hand, one known example of memory that allows more integration than SRAM is DRAM (Dynamic Random Access Memory). However, since DRAM adopts operation principles of storing charge in a capacitor and ensures a certain amount of capacitance or more in a fine cell area, it is indispensable to introduce a high-permittivity material, such as Ta2O5 (tantalum pentoxide), and a three-dimensional structure. Such DRAM has poor process consistency with logic transistors which form peripheral circuits of memory and other logical circuits.
To get around the problem, one suggested example of structure for DRAM operable without using a special capacitor structure is a structure of a storage element called a gain cell (gain-cell structure). This gain cell is a memory cell in which a storage node (charge-storage node) is charged via a write transistor and reading is performed by using the fact that conductance of a read transistor separately provided is varied by this stored charge.
Technologies regarding the gain-cell structure are disclosed in Japanese Patent Laid-Open Publication No. 2000-269457 and Japanese Patent Laid-Open Publication No. 2002-094029. Also, H. Shichijo et al, Conference on Solid State Devices and Materials, pp. 265-268, (1984) discloses a technology of applying polycrystalline silicon (polysilicon) to a write transistor. Furthermore, S. Shukuri et al, IEEE International Electron Devices Meeting, pp. 1006-1008, (1992) discloses a technology of applying polycrystalline silicon (polysilicon) to a read transistor. Still further, T. Osabe et al, IEEE International Electron Devices Meeting, pp. 301-304, (2000) discloses a technology regarding memory having a gain-cell structure with a sufficient retention time by utilizing the fact that a leakage current of a TFT (Thin Film Transistor) using an ultra-thin polycrystalline silicon film as a channel is extremely small.
As described above, compared with SRAM (Static Random Access Memory) that has been used as on-chip memory, DRAM (Dynamic Random Access Memory) using a memory cell having a gain-cell structure is more promising in high integration.